With the development of electronic display technologies, flat panel display devices such as active-type light emitting diode (LED) liquid crystal display (LCD) devices are widely applied into electronic devices.
A driving circuit as an essential part of the liquid crystal display device generally includes multiple gate driver integrated circuits (ICs). For the liquid crystal display device with half source driving (HSD) structure in which pixels are arranged in zigzag manner, an gate enable time is half shorten with respect to the other type LCD devices, so that when a source line changes display data signals thereon, it would easily cause wrongly charged voltages for pixels because of incompletely turned off gate pulses, resulting in line mura in displayed images. In addition, since the arrangement of gate lines and source lines, signal delays are caused so that the phenomenon of H-block occurred.
In order to solve the issue of line mura, a sloping circuit generally is used in the prior art to modulate the waveforms of gate pulses, so as to relieve the effect of the distortion of gate pulses applied to the image brightness of left-sided and right-sided pixels of a single source line.
However, since wires between gate driver ICs are formed in wire on array (WOA) manner, such wires cause the delay of output enable (OE) signal for the gate driver ICs, which would result in that different gate driver ICs have different feed-through and sloped voltages. As a result, output signals from different gate driver ICs would have a voltage difference (ΔV), resulting in the occurrence of color unevenness caused by H-band or 3-band in displayed images.
Referring to FIG. 1, waveforms of output signals of gate driver ICs and their waveform differences in the prior art are shown. Two gate driver ICs Y1, Y2 are taken as an example, in the prior art, since the wire layout between the gate driver ICs, the time of an output enable signal OE arriving at the gate driver IC Y1 is later than the time of the output enable signal OE arriving at the gate driver IC Y2 on the assumption of the transmission path of output enable signal being firstly passing through the gate driver IC Y2 and then arriving at the gate driver IC Y1, so that turned-on times of the respective gate driver ICs are different times with respect to a sloping voltage VGG1, and therefore a voltage difference is consequently produced between sloped portions of gate control signals G1, G2 outputted from the respective gate driver ICs Y1, Y2, i.e., V1 is not equal to V2 as illustrated in FIG. 1.
In order to relieve the above-described voltage difference, a conventional solution is to lengthen the period of logic low level of the output enable signal OE. However, in such HSD-type display device, a high-speed scanning operation is necessary, so that the conventional solution would cause the gate enable time being excessively short, resulting in more insufficient charging time of display data signal.
In short, due to the delay of output enable signal, the issues such as different turned-on times of gate driver ICs, signals being wrongly charged, and the sloped voltage difference between different gate control signals are raised.